The present invention relates generally to transistor devices and, more particularly, to low power and ultra-low power MOS devices including low power supply gating transistors.
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor components and systems. To meet this demand, devices are emerging which have extremely low threshold voltages. Low threshold voltage devices use less power for active operation and are typically faster. However, in addition to low active power usage, it is also important that the devices have very small power dissipation in a standby mode, i.e., that the devices have very small leakage currents and, therefore, use very little power in standby mode.
There are a number of factors that contribute to the magnitude of a transistor""s threshold voltage. For example, to set a transistor""s threshold voltage near zero, light doping and/or counter doping in the channel region of the transistor may be provided. Lowering the threshold voltage of a transistor typically decreases active power dissipation by permitting the same performance to be achieved at a lower supply voltage. However, lowering the threshold voltage of a transistor normally increases standby power dissipation by increasing transistor leakage current. Consequently, devices having low threshold voltages can leak so much current when their circuits are in a sleep or standby mode that the gains made by lowering the threshold voltage are outweighed by the power lost to leakage.
In the discussion that follows, an NFET is used as an example. However, those of skill in the art will readily recognize that a PFET will behave in essentially the same manner with reversed polarities. An NFET is therefore chosen for simplicity and to avoid detracting from the invention.
FIG. 1A is a schematic representation of a typical transistor 101 having a drain 103, a source 105 and a gate 107. As is well known in the art, if transistor 101 is an NFET, then transistor 101 is typically in an xe2x80x9coffxe2x80x9d or xe2x80x9cstandbyxe2x80x9d condition when the voltage on gate 107 (Vg) is sufficiently below a threshold voltage (Vth). However, as is also well known in the art, even when transistor 101 is in the xe2x80x9coffxe2x80x9d or xe2x80x9cstandbyxe2x80x9d state, there is still a leakage current from drain 103 to source 105.
FIG. 1B graphically represents the curve 110 of the voltage between the gate and the source (Vgs), on the horizontal axis 115, versus the log of the current between the drain and the source (Ids), on the vertical axis 117, for a typical prior art standard CMOS NFET transistor. As seen in FIG. 1B, Ids has a minimal value 113 in portion 119 of curve 110, as Vgs approaches zero volts and the transistor is driven into standby mode. However, Ids remains at minimal value 113 and is therefore typically never brought down to zero amps, even as Vgs goes negative. In portion 121 of curve 110, Ids increases exponentially to point 111 when Vgs is equal to Vth. After Vth is reached, and the transistor is in active mode, Ids increases as a quadratic function along portion 123 of curve 110 and substantially levels off from point 125 forward.
In a typical standard CMOS NFET, the leakage current, i.e., the current at point 113 in FIG. 1B is on the order of one pico-ampere (10xe2x88x9212 ampere) per micron. In addition, some newer transistors have 0.18-micron feature sizes and have leakage currents on the order of a nanoamp (10xe2x88x929 ampere) per micron. Consequently, devices including one hundred million of these new transistors and using a standard 1.8 volt supply voltage leak on the order of 0.1 ampere and dissipate 180 milliwatts of power in standby.
While the leakage currents discussed for standard CMOS transistors are less than ideal, they were largely tolerated in the prior art and, in standard CMOS, were not considered a fatal flaw. As discussed in more detail below, for low threshold transistors, leakage currents are not only significant but are a fatal flaw that can completely overshadow the advantages of these transistors and make them unworkable components.
Returning to the discussion of standard CMOS devices, if it were necessitated, one method to reduce the leakage current in standard CMOS would be to provide gating transistors to isolate the device from the voltage sources. FIG. 2 shows a prior art supply gated device 200 including a device 201, a first prior art gate transistor 203, coupled between first supply voltage 207 and device 201, and a second prior art gate transistor 205, coupled between device 201 and a second supply voltage 209. Device 201 could be any one of numerous devices well known to those of skill in the art such as a single transistor, an inverter, a latch, any one of several gates, or any other logic or memory devices. In FIG. 2, prior art gate transistor 203 is a PFET and includes a source 211, a gate 213 and a drain 215. Likewise, in FIG. 2, prior art gate transistor 205 is an NFET and includes a drain 221, a gate 223 and a source 225.
In standard CMOS, the difference in potential between first supply voltage 207 and second supply voltage 209 was on the order of two (2.0) volts. In one embodiment, first supply voltage 207 was a positive two-volt supply while second supply voltage 209 was ground, thus giving the typical two-volt differential.
The addition of prior art gating transistors 203 and 205 to device 201 helped control leakage current by providing a capability to isolate device 201 from first supply voltage 207 and second supply voltage 209. This capability was provided by using prior art gating transistors 203 and 205 as switches controlled by a voltage supplied to gates 213 and 223 of prior art gating transistors 203 and 205, respectively. Unfortunately, the addition of prior art gating transistors 203 and 205 meant that an additional transistor was added to each current path, i.e., prior art gating transistors 203 and 205 each added a resistance in series to the path between device 201 and the first and second supply voltages 207 and 209, respectively. This added resistance meant decreased performance and decreased device speed. The performance reduction due to the addition of prior art gating transistors 203 and 205 could be partially offset by increasing the size of prior art gating transistors 203 and 205 relative to the size of the transistors making up device 201. However, even a ten fold increase in relative size of prior art gating transistors 203 and 205 compared to the transistors in device 201 would still typically yield a decrease in performance of about ten percent for gated device 200 compared with a non-gated device.
A theoretical way to minimize the decrease in performance of device 201 due to the addition of prior art gating transistors 203 and 205 would be to drive prior art gating transistors 203 and 205 at a higher voltage than the voltage driving device 201. However, in practice, to actually make any significant difference in the performance, i.e., to significantly decrease the resistance added by prior art gating transistors 203 and 205, the supply voltages of prior art gating transistors 203 and 205 would need to be multiples, and preferable an order of magnitude, larger than the differential between first supply voltage 207 and second supply voltage 209. However, as noted above, in standard 0.18 micron CMOS technology, the voltage differential between first supply voltage 207 and second supply voltage 209 is on the order of two volts, the maximum tolerated over time by the 36 angstrom gate oxide. Consequently, the voltage differential required to significantly decrease the added resistance of prior art gating transistors 203 and 205 could not be withstood by standard CMOS transistors over time and prior art gating transistors 203 and 205 would eventually break down.
As discussed above, the addition of prior art gating transistors 203 and 205 would significantly decrease performance of device 201. Consequently, in the prior art, other techniques such as clock gating, i.e., isolating the device from the system clock as opposed to isolating the device from the supply voltages, were used. In large part however, the problem of leakage current was not considered a significant problem in prior art standard CMOS because the threshold voltages were relatively high and leakage current was not large (see point 113 of curve 110 in FIG. 1A). Indeed, the performance of prior art standard CMOS transistors was typically tailored to meet a predetermined and acceptable level of leakage current required to meet standby power limits.
As noted above, the level of leakage current in prior art standard CMOS transistors and devices was considered acceptable. However, as also noted above, it is highly desirably to lower the threshold voltage of a transistor to decrease active power dissipation by permitting the same performance to be achieved at a lower supply voltage. However, lowering the threshold voltage of a transistor normally increases standby power dissipation by increasing leakage current and devices having low threshold voltages can leak so much current when their circuits are in a sleep or standby mode that the gains made by lowering the threshold voltage are outweighed by the power lost to leakage.
FIG. 3 graphically represents the curve 310 of the voltage between the gate and the source (Vgs), on the horizontal axis 315, versus the log of the current between the drain and the source (Ids), on the vertical axis 317, for a typical low threshold NFET. Note that curve 310 for a low threshold NFET in FIG. 3 has substantially the same shape as curve 110 for a standard CMOS NFET shown in FIG. 1A. However, curve 310 in FIG. 3 is essentially shifted to the left as a result of lowering the threshold voltage of the device. As seen in FIG. 3, Ids has a minimal value 313 in portion 319 of curve 310. However, in FIG. 3, minimum value 313, and portion 319, lies in the region of curve 310 where Vgs is negative. Consequently, as Vgs approaches zero volts and the transistor is driven into standby mode, the Ids value 311 is relatively high. As a result, leakage current is also relatively high. This is in contrast to minimum value 113 for a standard CMOS transistor, as shown in FIG. 1B, which is reached as Vgs moves towards zero and the transistor goes into standby mode. In addition, in FIG. 3, portion 321 of curve 310, where Ids increases exponentially to point 311, i.e., to the point where Vgs is equal to Vth, is also almost entirely in the portion of curve 310 where Vgs is negative. This too is in direct contrast to curve 110 of FIG. 1B. In FIG. 3, after Vth is reached, and the transistor is in active mode, Ids increases as a quadratic function along portion 323 of curve 310 and substantially levels off from point 325 forward.
In a typical low threshold NFET, the leakage current, i.e., the current at point 313 in FIG. 3 is on the order of one microamp (10xe2x88x926 ampere) per micron. In contrast, recall that in standard CMOS devices the leakage-current was on the order of one pico-ampere to one nanoamp per micron (10xe2x88x9212 to 10xe2x88x929 ampere). Consequently, devices having one hundred million low threshold transistors and using a low power supply voltage of 200 millivolts, dissipate on the order of twenty (20.0) watts of power in standby. Clearly, this is not acceptable in many applications.
As shown above, it is particularly desirable in low-threshold devices to provide a mechanism for modulating the threshold voltage to account for variations. Modulating the threshold voltage of a device can be accomplished using back biasing, i.e. controlling the potential between a device""s well and source. See James B. Burr, xe2x80x9cStanford Ultra-Low Power CMOS,xe2x80x9d Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated, in its entirety, herein by reference. Back biasing is used to modulate the threshold voltages of the transistors between an off state and an on state. Typically, the potential will be controlled through isolated contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions.
While modulating the threshold voltage using back biasing provides a mechanism for at least partially controlling leakage current in a low power device, there are definite limits to the ability to significantly decrease leakage current using back biasing alone. This is because the use of back biasing to control leakage current relies on the well-known body effect of the device and the body effect decreases with a decrease in threshold voltage. Consequently, the ability to modulate the threshold voltages of the transistors between an off state and an on state, and therefore to control leakage current using back biasing alone, decreases as the threshold voltage decreases.
What is needed is a method and apparatus for decoupling the power dissipation of a device in standby mode from leakage current by using circuitry to control the leakage current in low threshold transistors and devices.
According to the invention, low power devices are provided with low threshold gating transistors. According to the invention, the low power devices operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors according to the invention, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one of, or a combination of, four methods.
First, since the devices of the invention are low power, and the supply voltages are so low, the gating transistors of the invention can be overdriven on, i.e., provided gate to source voltages (Vgs) significantly larger than the device supply voltage, in one embodiment tens times as large, without causing the destruction of the gating transistor. For instance, in one embodiment of the invention, the device supply voltage is 200 millivolts while the Vgs is on the order of 2.0 volts. This is in direct contrast to prior art gating transistors that had to be driven at essentially the same Vgs as the supply voltage to avoid transistor breakdown. By overdriving the gating transistors of the invention, the resistance added to the device by the gating transistors is decreased significantly without resorting to increasing the size of the transistor, as was done in the prior art. In addition, if even less resistance is desired, the size of the gating transistors of the invention can be increased and the transistor can still be overdriven according to the invention. Consequently, using the invention, there is an approach for resistance reduction available that was not available in the prior art and can provide orders of magnitude decrease in added resistance. Therefore, the invention can provide the advantages of supply gating without the large performance penalty associated with the prior art.
Second, since the threshold voltages of the supply gating transistors of the invention are so low, the gating transistors of the invention can be overdriven off to further decrease leakage. Indeed, a negative gate voltage of as little as xe2x88x92200 millivolts can reduce leakage by three orders of magnitude or more. By overdriving the gating transistors of the invention off, the transistor can be forced into an off condition where the leakage current is optimized. For instance, using an NFET low threshold gating transistor, Vgs can be made negative so that the drain to source current (Ids) is forced into a negative Vgs regime where Ids decreases exponentially. This improvement is possible because, according to the invention, and unlike the prior art, the gating transistors are low threshold devices.
Third, according to one embodiment of the invention, two types of low threshold transistors are employed; a first type having a threshold voltage of approximately zero volts (0.0 volts) and a second type having a threshold voltage of approximately one hundred and fifty millivolts (150 millivolts). In this embodiment of the invention, the low threshold transistors of the first type, i.e., the Vth1 transistors, are used within the low power device while the low threshold transistors of the second type, i.e., the Vth2 transistors, are used as gating transistors. Since, in this embodiment of the invention, the gating transistors have higher threshold voltages (Vth2) than the device transistors"" threshold voltages (Vth1), the gating transistors have lower leakage and provide a gating function to isolate the low power device from the supply voltages. However, since the gating transistors of this embodiment of the invention still have threshold voltages significantly lower than prior art gating transistors, the resulting gated device is still a low power device with decreased active power dissipation and the same performance at a lower supply voltage.
Fourth, in one embodiment of the invention, the low threshold gating transistors are provided with back bias to modulate the threshold voltages of the first and second low threshold gating transistors between an off state and an on-state. The use of back bias is particularly advantageous with embodiments of the invention where low threshold transistors of the second type, i.e., the Vth2 transistors discussed above, are used as the gating transistors. This is because, as discussed above, higher threshold voltages means the device exhibits more body effect and more body effect means that back biasing is more effective. In one embodiment of the invention, the low threshold gating transistors are each provided with a separate back bias from a back bias that is provided to the transistors of the device.
The four methods of reducing leakage current using the invention discussed above are by no means mutually exclusive and it is anticipated that they will be used in combination to achieve the desired results. In one embodiment of the invention, all four methods are employed in a single device.
In particular, according to the invention, a method for supply gating an electronic component includes: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second low threshold gating transistor is coupled between the at least one device and the second supply voltage. In one embodiment, the first and second low threshold gating transistors have an unbiased threshold voltage with a magnitude of about 300 millivolts. The invention includes overdriving the first and second low threshold gating transistors on such that when the first and second low threshold gating transistors are in an on state, a voltage differential between a gate and a source of the first and second low threshold gating transistors is greater than a voltage differential between the first and second supply voltages.
In one embodiment of the invention, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than about 1.0 volt. In this embodiment, the voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven on is less than 2.5 volts.
In one embodiment of the invention, the device transistors have a first unbiased threshold voltage and the low threshold gating transistors have a second unbiased threshold voltage, different from the first unbiased threshold voltage, and the first unbiased threshold voltage is lower than the second unbiased threshold voltage.
In another embodiment of the invention, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than 400 millivolts. In this embodiment, the voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven on is less than 2.5 volts and the first and second low threshold gating transistors each have an unbiased threshold voltage with a magnitude of about 250 millivolts.
In one embodiment of the invention, a method for supply gating an electronic component includes: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first back biased low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second back biased low threshold gating transistor is coupled between the at least one device and the second supply voltage. The first and second back biased low threshold gating transistors each has an unbiased threshold voltage with a magnitude of about 250 millivolts. In this embodiment, a back bias potential is applied to the first and second back biased low threshold gating transistors to modulate the threshold voltages of the first and second low threshold gating transistors between an off-state and an on-state.
One embodiment of the invention is a method for supply gating an electronic component that includes: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second low threshold gating transistor is coupled between the at least one device and the second supply voltage. The first and second low threshold gating transistors each have an unbiased threshold voltage having a magnitude of about 250 millivolts. The first and second low threshold gating transistors are overdriven off. In one embodiment of the invention, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than about 1.0 volt. In this embodiment of the invention, the magnitude of voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven off is less than 500 millivolts. In one embodiment of the invention, the device transistors have a first unbiased threshold voltage and the low threshold gating transistors have a second unbiased threshold voltage, different from the first unbiased threshold voltage, wherein the first unbiased threshold voltage is lower than the second unbiased threshold voltage.
In another embodiment of the invention, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than about 400 millivolts. In this embodiment of the invention, the voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven off is less than 200 millivolts and the first and second low threshold gating transistors each have an unbiased threshold voltage having a magnitude of about 250 millivolts.
According to another embodiment of the invention, a method for supply gating an electronic component includes: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first back biased low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second back biased low threshold gating transistor is coupled between the at least one device and the second supply voltage. In one embodiment, the first and second back biased low threshold gating transistors each have an unbiased threshold voltage with a magnitude of about 250 millivolts. A separate back bias potential is applied to the first and second back biased low threshold gating transistors to modulate a threshold voltage of the first and second low threshold gating transistors between an on and an off state. The first and second back biased low threshold gating transistors are overdriven off.
In another embodiment of the invention, a method for supply gating an electronic component includes: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second low threshold gating transistor is coupled between the at least one device and the second supply voltage. In one embodiment, the first and second low threshold gating transistors each have an unbiased threshold voltage with a magnitude of about 250 millivolts. The first and second low threshold gating transistors are overdriven on such that when the first and second low threshold gating transistors are in an on state, a voltage differential between a gate and a source of the first and second low threshold gating transistors is greater than a voltage differential between the first and second supply voltages. The first and second low threshold gating transistors are also overdriven off. In one embodiment of the invention, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than about 1.0 volt. In this embodiment, the voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven on is less than 2.5 volts and the voltage differential between the gate and the source of the first and second low threshold gating transistors when the first and second low threshold gating transistors are overdriven off is less than 200 millivolts volts. In one embodiment, the device transistors have a first unbiased threshold voltage and the low threshold gating transistors have a second unbiased threshold voltage, different from the first unbiased threshold voltage, wherein the first unbiased threshold voltage is lower than the second unbiased threshold voltage.
Another embodiment of the invention includes a method for supply gating an electronic component by: providing a first supply voltage; providing at least one device; and providing a second supply voltage. A first back biased low threshold gating transistor is coupled between the first supply voltage and the at least one device. A second back biased low threshold gating transistor is coupled between the at least one device and the second supply voltage. The first and second back biased low threshold gating transistors each have an unbiased threshold voltage with a magnitude of about 200 millivolts and a back bias potential is applied to the first and second back biased low threshold gating transistors to modulate the threshold voltages of the first and second low threshold gating transistors between an off-state and an on-state. The first and second back biased low threshold gating transistors are overdriven on such that when the first and second back biased low threshold gating transistors are in an on state, a voltage differential between a gate and a source of the first and second back biased low threshold gating transistors is greater than a voltage differential between the first and second supply voltages. The first and second low threshold gating transistors are also overdriven off. In one embodiment, the at least one device is a low power device including device transistors and the voltage differential between the first supply voltage and the second supply voltage is less than 250 millivolts. In this embodiment, the voltage differential between the gate and the source of the first and second back biased low threshold gating transistors when the first and second back biased low threshold gating transistors are overdriven on is less than 2.5 volts and the voltage differential between the gate and the source of the first and second back biased low threshold gating transistors when the first and second back biased low threshold gating transistors are overdriven off is less than 0.2 volts. In this embodiment, the first and second low threshold gating transistors each have an unbiased threshold voltage with a magnitude of about 250 millivolts. In one embodiment, the device transistors have a first unbiased threshold voltage and the back biased low threshold gating transistors have a second unbiased threshold voltage, different from the first unbiased threshold voltage, wherein the first unbiased threshold voltage is lower than the second unbiased threshold voltage.
According to the invention, the low threshold gating transistors can be overdriven on so that the resistance added by including gating transistors is minimized and device performance is enhanced. This is in contrast to the prior art gating transistors that added significant resistance and decreased performance in terms of decreased device speed. In one embodiment of the invention, the performance enhancement of the present invention is obtained, in contrast to the prior art, without increasing the size of the gating transistors relative to the size of the transistors making up the device. In addition, if even less resistance is desired, according to the invention, the size of gating transistors of the invention can be increased and the transistor can still be overdriven on according to the invention. Therefore, the invention can provide the advantages of supply gating without the large performance penalty associated with the prior art.
In addition, the gating transistors of the invention can be overdriven off. By overdriving the gating transistors of the invention off, the transistor can be forced into an off condition where the leakage current is optimized.
In addition, according to one embodiment of the invention, low threshold transistors of a first type are used within the low power device while the low threshold transistors of the second type are used as gating transistors. Since, in this embodiment of the invention, the gating transistors have higher threshold voltages than the device transistors, the gating transistors have lower leakage and provide a gating function to isolate the low power device from the supply voltages.
In one embodiment of the invention, the low threshold gating transistors are provided with back bias to modulate the threshold voltages of the first and second low threshold gating transistors between an off state and an on-state. The use of back bias is particularly advantageous with embodiments of the invention where low threshold transistors of the second type, discussed above, are used as the gating transistors. This is because, as discussed above, a higher threshold voltage means the transistor exhibits more body effect and more body effect means that back biasing is more effective.
Consequently, using the method and apparatus of the invention, the power dissipation of a device in standby mode is decoupled from leakage current by using circuitry to control the leakage current in low threshold transistors and devices. Therefore, using the invention, the threshold voltage of a device is lowered and the active power dissipation is decreased by permitting the same performance to be achieved at a lower supply voltage. However, using the invention, the increase in device leakage current and standby power dissipation typically associated with lowered threshold voltage of a device is avoided.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.